{"ok":true,"nota":{"id":"6ce8f1dcbeba3c51","slug":"un-metodo-nuevo-permite-disenar-chips-reconfigurables-para-sistemas-qu-6ce8f1","titulo":"Un método nuevo permite diseñar chips reconfigurables para sistemas que deben responder en tiempo real","resumen":"Se presentó FoRTReSS, una metodología para diseñar arquitecturas de hardware que pueden reconfigurarse parcialmente mientras funcionan y que deben cumplir plazos estrictos. La herramienta se probó con una aplicación de cifrado de video.","fuente":"hal","fuenteNombre":"HAL · Ciencia abierta","color":"#b06000","autor":"Duhem, F., Muller, Fabrice, Aubry, Willy","url":"https://hal.science/hal-00998839","imagen":"/hoy/portada/6ce8f1dcbeba3c51","tema":"tecnologia","subtemas":["chips reconfigurables","sistemas en tiempo real","diseño de hardware","cifrado de video","ingenieria electronica"],"entidades":["FoRTReSS","HAL"],"formato":"dato","entretenimiento":false,"pubTs":"2026-10-23T00:00:00.000Z","indexTs":"2026-10-23T12:03:18.527Z","hash":"d408ad5540c5a5570fd9eec1d655e8e6e041cb0b01ea38275484ab955ae7b4bc","tsa":{"time":"Oct 23 12:04:20 2026 GMT","provider":"freetsa.org","sobre":"sello"},"stats":{"views":0,"likes":0,"clicks":0,"dwell":0},"tipo":"normal","registro":"hallazgo","porQueImporta":"Los dispositivos que procesan video, comunicaciones o control industrial necesitan respuestas en fracciones de segundo, y poder cambiar partes de su hardware sin apagarlos ahorra energía y espacio. Esta herramienta busca que los ingenieros puedan evaluar esas decisiones antes de fabricar el chip, lo que reduce errores y costos. Para alguien fuera del área, es un avance técnico que se nota en los equipos que usa todos los días, aunque no se vea.","quienFirma":"HAL (repositorio abierto de publicaciones científicas francesas)","confianza":"revisado","consulta":null},"sello":{"hash":"d408ad5540c5a5570fd9eec1d655e8e6e041cb0b01ea38275484ab955ae7b4bc","sello":"19e860f4db868e2d0f3c1559baf8d6bc74685fdfafc4245870e331d44f054931","beacon":{"drand":{"cadena":"8990e7a9aaed2ffed73dbd7092123d6f289930540d7651336225dc172e51b2ce","ronda":6577534,"aleatorio":"c9e07c4a7baaade0e8acc56f64536cbb18d3ad1e3d8c1ae5596009491ca1c705","tiempo":"2026-10-23T12:04:00.000Z"},"nist":{"cadena":2,"pulso":1995961,"salida":"F41B5D0D554B9AA93D86596521336D547B043E4F52A3C280F10F60EAE511ED1743D3E56670D4E53EB431734AC5B1B8CB5DCF96D1DB26F562D058604979415129","tiempo":"2026-10-23T12:03:00.000Z"},"noAntes":"2026-10-23T12:04:00.000Z"},"verificacion":{"drand":true,"nist":true},"tsa":{"time":"Oct 23 12:04:20 2026 GMT","provider":"freetsa.org","sobre":"sello"},"original":{"titulo":"Design Space Exploration for Partially Reconfigurable Architectures in Real-Time Systems","descripcion":"In this paper, we introduce FoRTReSS (Flow for Reconfigurable archiTectures in Real-time SystemS), a methodology for the generation of partially reconfigurable architectures with real-time constraints, enabling Design Space Exploration (DSE) at the early stages of the development. FoRTReSS can be completely integrated into existing partial reconfiguration flows to generate physical constraints describing the architecture in terms of reconfigurable regions that are used to floorplan the design, with key metrics such as partially reconfigurable area, real-time or external fragmentation. The flow is based upon our SystemC simulator for real-time systems that helps develop and validate scheduling algorithms with respect to application timing constraints and partial reconfiguration physical behaviour. We tested our approach with a video stream encryption/decryption application together with E","pubDate":"2026-10-23","url":"https://hal.science/hal-00998839"},"indexado":"2026-10-23T12:03:18.527Z"}}